diff -r -u5 -N -x '*~' insight-5.3/gdb/config/h8300/tm-h8300.h insight-5.3-H8/gdb/config/h8300/tm-h8300.h --- insight-5.3/gdb/config/h8300/tm-h8300.h 2002-08-24 01:21:35.000000000 +0100 +++ insight-5.3-H8/gdb/config/h8300/tm-h8300.h 2003-04-03 10:24:18.000000000 +0100 @@ -86,12 +86,11 @@ /* Stack grows downward. */ #define INNER_THAN(lhs,rhs) ((lhs) < (rhs)) -/*#define BREAKPOINT {0x7A, 0xFF} */ -#define BREAKPOINT {0x01, 0x80} /* Sleep */ +#define BREAKPOINT {0x7A, 0xFF} #define REMOTE_BREAKPOINT { 0x57, 0x30} /* trapa #3 */ /* If your kernel resets the pc after the trap happens you may need to define this before including this file. */ #define DECR_PC_AFTER_BREAK 0 diff -r -u5 -N -x '*~' insight-5.3/sim/h8300/Makefile.in insight-5.3-H8/sim/h8300/Makefile.in --- insight-5.3/sim/h8300/Makefile.in 2002-07-29 18:01:57.000000000 +0100 +++ insight-5.3-H8/sim/h8300/Makefile.in 2003-04-10 16:41:04.000000000 +0100 @@ -16,11 +16,11 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ## COMMON_PRE_CONFIG_FRAG -SIM_OBJS = compile.o sim-load.o +SIM_OBJS = compile.o sim-load.o io.o ## COMMON_POST_CONFIG_FRAG compile.o: compile.c inst.h config.h \ $(srcdir)/../../include/gdb/sim-h8300.h \ $(srcdir)/../../include/gdb/remote-sim.h \ diff -r -u5 -N -x '*~' insight-5.3/sim/h8300/compile.c insight-5.3-H8/sim/h8300/compile.c --- insight-5.3/sim/h8300/compile.c 2002-07-29 18:01:57.000000000 +0100 +++ insight-5.3-H8/sim/h8300/compile.c 2003-04-17 17:38:58.000000000 +0100 @@ -38,10 +38,12 @@ #ifndef SIGTRAP # define SIGTRAP 5 #endif +#define fprintf + int debug; host_callback *sim_callback; static SIM_OPEN_KIND sim_kind; @@ -332,10 +334,14 @@ { plen = 3; bit = thisnib; } + else if (looking_for & (L_2 | IMM)) + { + plen = 1; + } else if (looking_for == E) { dst->op = q; /* Fill in the args. */ @@ -982,10 +988,12 @@ int bit; int pc; int c, nz, v, n, u, h, ui, intMaskBit; int trace, intMask; int oldmask; + int vector; + init_pointers (); prev = signal (SIGINT, control_c); if (step) @@ -1042,10 +1050,39 @@ } cpu.stats[code->opcode]++; #endif +#define INT_ENABLE \ + ((!h8300smode && intMaskBit == 0) || \ + (h8300smode && intMask < 7)) + + if ((vector=iosimulation(&cpu,cycles)) && INT_ENABLE) + { + fprintf(stderr, "%s %d: INT vector %d\n",__FUNCTION__,__LINE__,vector); + BUILDSR(); + cpu.regs[7]-=4; + fprintf(stderr, "%s %d: INT pc %08x ccr %02x \n",__FUNCTION__,__LINE__,pc,cpu.ccr); + SET_MEMORY_L(cpu.regs[7],(cpu.ccr<<24)|pc); + pc=GET_MEMORY_L(vector*(h8300hmode?4:2)); + if (h8300smode) { + int exr; + BUILDEXR(); + exr = cpu.exr << 8 | cpu.exr; + cpu.regs[7]-=2; + SET_MEMORY_W(cpu.regs[7],exr); + cpu.exr |= 0x07; + intMask = 0x07; +fprintf(stderr, "%s %d: INT cpu.exr %04x exr %04x\n",__FUNCTION__,__LINE__,cpu.exr,exr); + } + cpu.ccr|=0x80; + intMaskBit = 1; +// fprintf(stderr, "%s %d: INT saved %08x \n",__FUNCTION__,__LINE__,GET_MEMORY_L(cpu.regs[7])); + fprintf(stderr, "%s %d: INT sp %08x pc %08x ccr %02x \n",__FUNCTION__,__LINE__,cpu.regs[7],pc,cpu.ccr); + goto top; + } + if (code->opcode) { cycles += code->cycles; insts++; } @@ -1481,10 +1518,11 @@ case O (O_ILL, SB): cpu.state = SIM_STATE_STOPPED; cpu.exception = SIGILL; goto end; case O (O_SLEEP, SN): +#if 0 /* FIXME: Doesn't this break for breakpoints when r0 contains just the right (er, wrong) value? */ cpu.state = SIM_STATE_STOPPED; /* The format of r0 is defined by target newlib. Expand the macros here instead of looking for .../sys/wait.h. */ @@ -1492,10 +1530,37 @@ #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f)) if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED (cpu.regs[0])) cpu.exception = SIGILL; else cpu.exception = SIGTRAP; +#endif + if (!INT_ENABLE) + { + cpu.state = SIM_STATE_STOPPED; + cpu.exception = SIGTRAP; + } else + while (cpu.state = SIM_STATE_RUNNING) { + if ((vector=iosimulation(&cpu,cycles)) && !(cpu.ccr & 0x80)) + { + usleep(100); + BUILDSR(); + BUILDEXR(); + cpu.regs[7]-=4; + SET_MEMORY_L(cpu.regs[7],(cpu.ccr<<24)|pc+2); + pc=GET_MEMORY_L(vector*(h8300hmode?4:2)); + if (h8300smode) { + int exr; + exr = cpu.exr << 8 | cpu.exr; + cpu.regs[7]-=2; + SET_MEMORY_W(cpu.regs[7],exr); + intMask = 0x07; + } + intMaskBit = 1; + goto top; + } + cycles++; + } goto end; case O (O_BPT, SN): cpu.state = SIM_STATE_STOPPED; cpu.exception = SIGTRAP; goto end; @@ -1669,10 +1734,51 @@ cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]); cpu.regs[7] += 4; } } goto next; + case O (O_RTE, SN): + { + unsigned int frame; + if (h8300smode) { + unsigned int exr; + exr = GET_MEMORY_W (cpu.regs[7]); + exr >>= 8; + exr &= 0xff; + cpu.exr = exr; + cpu.regs[7]+=2; + fprintf(stderr, "%s %d: RTE exr %08x\n",__FUNCTION__,__LINE__,exr); + } + frame = GET_MEMORY_L (cpu.regs[7]); + fprintf(stderr, "%s %d: RTE sp %08x frame %08x\n",__FUNCTION__,__LINE__,cpu.regs[7],frame); + cpu.ccr=frame>>24; + GETSR(); + GETEXR(); + pc=frame & 0xffffff; + cpu.regs[7]+=4; + }; + fprintf(stderr, "%s %d: RTE pc %08x ccr %02x \n",__FUNCTION__,__LINE__,pc,cpu.ccr); + goto end; + case O (O_TRAPA, SB): + { + int v; + v=GET_MEMORY_W(pc)>>4; + v&=3; + BUILDSR(); + BUILDEXR(); + cpu.regs[7]-=4; + SET_MEMORY_L(cpu.regs[7],(cpu.ccr<<24)|code->next_pc); + pc=GET_MEMORY_L(v*(h8300hmode?4:2)+0x08*(h8300hmode?4:2)); + intMaskBit = 1; + if (h8300smode) { + int exr; + exr = cpu.exr << 8 | cpu.exr; + cpu.regs[7]-=2; + SET_MEMORY_W(cpu.regs[7],exr); + } + }; + goto end; default: illegal: cpu.state = SIM_STATE_STOPPED; cpu.exception = SIGILL; @@ -1993,12 +2099,12 @@ int v; int longreg = 0; init_pointers (); - if (!h8300smode && rn >=EXR_REGNUM) - rn++; +// if (!h8300smode && rn >=EXR_REGNUM) +// rn++; switch (rn) { default: abort (); case CCR_REGNUM: @@ -2148,34 +2254,41 @@ /* FIXME: Much of the code in sim_load can be moved to sim_open. This function being replaced by a sim_open:ARGV configuration option. */ h8300hmode = h_flag; h8300smode = s_flag; +fprintf(stderr, "%s %d: h8300hmode %d h8300smode %d \n",__FUNCTION__,__LINE__,h8300hmode,h8300smode); } SIM_DESC sim_open (kind, ptr, abfd, argv) SIM_OPEN_KIND kind; struct host_callback_struct *ptr; struct _bfd *abfd; char **argv; { /* FIXME: Much of the code in sim_load can be moved here. */ - + char *ptyname; +fprintf(stderr, "%s %d: kind %08x ptr %08x abfd %08x\n",__FUNCTION__,__LINE__,kind,ptr,abfd); sim_kind = kind; myname = argv[0]; sim_callback = ptr; + if((ptyname=openpty())!=NULL) + (*sim_callback->printf_filtered) (sim_callback, + "SCI0 = %s\n",ptyname); + /* Fudge our descriptor. */ return (SIM_DESC) 1; } void sim_close (sd, quitting) SIM_DESC sd; int quitting; { /* Nothing to do. */ + closepty(); } /* Called by gdb to load a program into memory. */ SIM_RC @@ -2185,27 +2298,31 @@ bfd *abfd; int from_tty; { bfd *prog_bfd; +fprintf(stderr, "%s %d: prog %s abfd %08x from_tty %d\n",__FUNCTION__,__LINE__,prog,abfd,from_tty); /* FIXME: The code below that sets a specific variant of the H8/300 being simulated should be moved to sim_open(). */ /* See if the file is for the H8/300 or H8/300H. */ /* ??? This may not be the most efficient way. The z8k simulator does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */ if (abfd != NULL) prog_bfd = abfd; else - prog_bfd = bfd_openr (prog, "coff-h8300"); +// prog_bfd = bfd_openr (prog, "coff-h8300"); + prog_bfd = bfd_openr (prog, "elf32-h8300"); +fprintf(stderr, "%s %d: prog_bfd %08x\n",__FUNCTION__,__LINE__,prog_bfd); if (prog_bfd != NULL) { /* Set the cpu type. We ignore failure from bfd_check_format and bfd_openr as sim_load_file checks too. */ if (bfd_check_format (prog_bfd, bfd_object)) { unsigned long mach = bfd_get_mach (prog_bfd); +fprintf(stderr, "%s %d: mach %08x\n",__FUNCTION__,__LINE__,mach); set_h8300h (mach == bfd_mach_h8300h || mach == bfd_mach_h8300s, mach == bfd_mach_h8300s); } } @@ -2245,10 +2362,11 @@ /* `msize' must be a power of two. */ if ((memory_size & (memory_size - 1)) != 0) abort (); cpu.mask = memory_size - 1; + init_ioregs(&cpu); if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd, sim_kind == SIM_OPEN_DEBUG, 0, sim_write) == NULL) { diff -r -u5 -N -x '*~' insight-5.3/sim/h8300/inst.h insight-5.3-H8/sim/h8300/inst.h --- insight-5.3/sim/h8300/inst.h 2002-05-17 20:19:24.000000000 +0100 +++ insight-5.3-H8/sim/h8300/inst.h 2003-04-03 10:24:18.000000000 +0100 @@ -18,11 +18,11 @@ /* avolkov: Next 2 macros are ugly for any workstation, but while they're work. Memory size MUST be configurable. */ -#define H8300H_MSIZE (1<<18) +#define H8300H_MSIZE (1<<24) #define H8300S_MSIZE (1<<24) #define CSIZE 1000 /* Local register names */ diff -r -u5 -N -x '*~' insight-5.3/sim/h8300/io.c insight-5.3-H8/sim/h8300/io.c --- insight-5.3/sim/h8300/io.c 1970-01-01 01:00:00.000000000 +0100 +++ insight-5.3-H8/sim/h8300/io.c 2003-04-16 15:04:16.000000000 +0100 @@ -0,0 +1,390 @@ +/* + H8 simulator Internal Peripheral Support +*/ + +#include +//#include +#include +#include +#include + +#include + +//#include "sim-basics.h" +//#include "sim-signal.h" +//#include "sim-io.h" + +#include "inst.h" + + +#define SMR (cpu->memory[sci_base+0]) +#define BRR (cpu->memory[sci_base+1]) +#define SCR (cpu->memory[sci_base+2]) +#define TDR (cpu->memory[sci_base+3]) +#define SSR (cpu->memory[sci_base+4]) +#define RDR (cpu->memory[sci_base+5]) + +#define TCR 0 +#define TCSR 2 +#define TCORA 4 +#define TCORB 6 +#define TCNT 8 + +static int scifd=-1; +//static struct termios old_attr; +static unsigned char ssr=0; +static unsigned int sci_base; + +extern int h8300hmode; +extern int h8300smode; + +static void timer8sub(const int base[], unsigned char tcsr[], int cyc, cpu_state_type *cpu, int ch) +{ + static int prescale[3]={8,64,8192}; + const int prescale_div[3]={8,64,8192}; + int tm,cnt,pcnt; + for (pcnt = 0; pcnt < 3; pcnt++) { + prescale[pcnt] -= cyc; + if (prescale[pcnt]<=0) + { + for(tm=0;tmmemory[base[tm]+TCSR] & 0xe0); + if ((cpu->memory[base[tm]+TCR]&0x07) == (pcnt+1)) + { + cnt=++cpu->memory[base[tm]+TCNT]; + if (cnt>=0x100) + { + tcsr[tm]|=0x20; + cnt=0; + } + cpu->memory[base[tm]+TCNT]=cnt; + } + if (cpu->memory[base[tm]+TCNT] >= cpu->memory[base[tm]+TCORA]) + { + tcsr[tm]|=0x40; + if ((cpu->memory[base[tm]+TCR]&0x18) == 0x08) + cpu->memory[base[tm]+TCNT] = 0; + } + if (cpu->memory[base[tm]+TCNT] >= cpu->memory[base[tm]+TCORB]) + { + tcsr[tm]|=0x80; + if ((cpu->memory[base[tm]+TCR]&0x18) == 0x10) + cpu->memory[base[tm]+TCNT] = 0; + } + cpu->memory[base[tm]+TCSR] &= 0x1f; + cpu->memory[base[tm]+TCSR] |= (tcsr[tm] & 0xe0); + } + prescale[pcnt]+=prescale_div[pcnt]; + } + } +} + +static void +h8300h_timer8(cpu_state_type *cpu,int cycles) +{ + static unsigned char tcsr[4]={0x00,0x00,0x00,0x00}; + const int base[4]={0xffff80,0xffff81,0xffff90,0xffff91}; + static unsigned int prev_cycle=0; + int cyc; + cyc=(unsigned int)cycles-prev_cycle; + prev_cycle=cycles; + timer8sub(base,tcsr,cyc,cpu,4); +} + +static void +h8300s_timer8(cpu_state_type *cpu,int cycles) +{ + static unsigned char tcsr[2]={0x00,0x00}; + const int base[2]={0xffffb0,0xffffb1}; + static unsigned int prev_cycle=0; + int cyc; + cyc=(unsigned int)cycles-prev_cycle; + prev_cycle=cycles; + timer8sub(base,tcsr,cyc,cpu,2); +} + +static unsigned int complete_time(cpu_state_type *cpu,int cycles) +{ + int length; + int div[]={1,4,16,64}; + length=(SMR & 0x40)?7:8; + length+=(SMR & 0x20)?1:0; + length+=(SMR & 0x08)?1:0; + length+=2; + return length*32*div[SMR & 0x03]*BRR+cycles; +} + +static void send_data(int txd) +{ + char dt; + dt=txd; +#if 1 + write(scifd,&dt,1); + fsync(scifd); +#else + sim_io_write_stdout((SIM_DESC)1, &dt, 1); + sim_io_flush_stdout((SIM_DESC)1); +#endif +} + +static int rcv_data(int *rxd) +{ +#if 0 + char rd; + if(read(scifd,&rd,1)>0) { + *rxd=rd; + return 1; + } else +#endif + return 0; +} + +static int sci(cpu_state_type *cpu,int cycles) +{ + static int tx_end_time=0; + static int rx_end_time=0; + static int data=-1; + ssr &= SSR; + if((SCR & 0x20) && !(ssr & 0x80)) { + send_data(TDR); + ssr |= 0x80; + tx_end_time=complete_time(cpu,cycles); + } + if ((data == -1) && !rcv_data(&data)) + data = -1; + if((data != -1) && (SCR & 0x10) && ((rx_end_time==0) || (rx_end_time-cycles)<0)) { + if(ssr & 0x40) { + ssr |= 0x20; + } else { + RDR=data; + ssr |= 0x40; + data=-1; + } + rx_end_time=complete_time(cpu,cycles); + } + if((tx_end_time>0) && (tx_end_time-cycles)<0) { + if(ssr & 0x80) { + ssr |= 0x04; + } + } + SSR = ssr; +} + +static int +h8300h_intcont(cpu_state_type *cpu) +{ +#if 1 + struct INT_LIST { + int vector; + int isr_adr; + unsigned char isr_mask; + int ier_adr; + unsigned char ier_mask; + } int_table[]= { + {36,0xffff82,0x40,0xffff80,0x40}, + {37,0xffff82,0x80,0xffff80,0x80}, + {38,0xffff83,0x40,0xffff81,0x40}, + {38,0xffff83,0x80,0xffff81,0x40}, + {39,0xffff82,0x20,0xffff80,0x20}, + {39,0xffff83,0x20,0xffff81,0x20}, + {40,0xffff92,0x40,0xffff90,0x40}, + {41,0xffff92,0x80,0xffff90,0x80}, + {42,0xffff93,0x40,0xffff91,0x40}, + {42,0xffff93,0x80,0xffff91,0x40}, + {43,0xffff92,0x20,0xffff90,0x20}, + {43,0xffff93,0x20,0xffff91,0x20}, + {52,0xffffb4,0x38,0xffffb2,0x40}, + {53,0xffffb4,0x40,0xffffb2,0x40}, + {54,0xffffb4,0x80,0xffffb2,0x80}, + {55,0xffffb4,0x04,0xffffb2,0x04} + }; + int irqno; + for (irqno=0;irqnomemory[int_table[irqno].ier_adr]&int_table[irqno].ier_mask) + if(cpu->memory[int_table[irqno].isr_adr]&int_table[irqno].isr_mask) + { +// fprintf(stderr, "%s %d: vector %d\n",__FUNCTION__,__LINE__,int_table[irqno].vector); + return int_table[irqno].vector; + } + } +#endif + return 0; +} + +static int +h8300s_intcont(cpu_state_type *cpu) +{ + struct INT_LIST { + int vector; + int isr_adr; + unsigned char isr_mask; + int ier_adr; + unsigned char ier_mask; + } int_table[]= { + {72,0xffffb2,0x40,0xffffb0,0x40}, + {73,0xffffb2,0x80,0xffffb0,0x80}, + {76,0xffffb3,0x40,0xffffb1,0x40}, + {77,0xffffb3,0x80,0xffffb1,0x40}, + {74,0xffffb2,0x20,0xffffb0,0x20}, + {78,0xffffb3,0x20,0xffffb1,0x20}, + {88,0xffff7c,0x38,0xffff7a,0x40}, + {89,0xffff7c,0x40,0xffff7a,0x40}, + {90,0xffff7c,0x80,0xffff7a,0x80}, + {91,0xffff7c,0x04,0xffff7a,0x04} + }; + int irqno; + for (irqno=0;irqnomemory[int_table[irqno].ier_adr]&int_table[irqno].ier_mask) + if(cpu->memory[int_table[irqno].isr_adr]&int_table[irqno].isr_mask) + return int_table[irqno].vector; + } + return 0; +} + +int +iosimulation(cpu_state_type *cpu,int cycles) +{ + if (h8300hmode && !h8300smode) h8300h_timer8(cpu,cycles); + if (h8300smode) h8300s_timer8(cpu,cycles); + sci(cpu,cycles); + if (h8300hmode && !h8300smode) return h8300h_intcont(cpu); + if (h8300smode) return h8300s_intcont(cpu); +} + +void init_ioregs(cpu_state_type *cpu) +{ + struct INITTABLE { + int addr; + short data; + }; + const struct INITTABLE h8300h_reg_ini[] = { + 0xffff80,0x00, + 0xffff81,0x00, + 0xffff82,0x00, + 0xffff83,0x00, + 0xffff84,0xff, + 0xffff85,0xff, + 0xffff86,0xff, + 0xffff87,0xff, + 0xffff88,0x00, + 0xffff89,0x00, + 0xffff90,0x00, + 0xffff91,0x00, + 0xffff92,0x00, + 0xffff93,0x00, + 0xffff94,0xff, + 0xffff95,0xff, + 0xffff96,0xff, + 0xffff97,0xff, + 0xffff98,0x00, + 0xffff99,0x00, + 0xffffb0,0x00, + 0xffffb1,0xff, + 0xffffb2,0x00, + 0xffffb3,0xff, + 0xffffb4,0x84, + 0xffffb8,0x00, + 0xffffb9,0xff, + 0xffffba,0x00, + 0xffffbb,0xff, + 0xffffbc,0x84, + 0xffffc0,0x00, + 0xffffc1,0xff, + 0xffffc2,0x00, + 0xffffc3,0xff, + 0xffffc4,0x84, + }; + const struct INITTABLE h8300s_reg_ini[] = { + 0xffffb0,0x00, + 0xffffb1,0x00, + 0xffffb2,0x00, + 0xffffb3,0x00, + 0xffffb4,0xff, + 0xffffb5,0xff, + 0xffffb6,0xff, + 0xffffb7,0xff, + 0xffffb8,0x00, + 0xffffb9,0x00, + 0xffff78,0x00, + 0xffff79,0xff, + 0xffff7a,0x00, + 0xffff7b,0xff, + 0xffff7c,0x84, + 0xffff80,0x00, + 0xffff81,0xff, + 0xffff82,0x00, + 0xffff83,0xff, + 0xffff84,0x84, + 0xffff88,0x00, + 0xffff89,0xff, + 0xffff8a,0x00, + 0xffff8b,0xff, + 0xffff8c,0x84, + }; + int c; + if (h8300hmode && !h8300smode) { + sci_base=0xffffb0; + for(c=0;cmemory[h8300h_reg_ini[c].addr]=h8300h_reg_ini[c].data; + } + if (h8300smode) { + sci_base=0xffff78; + for(c=0;cmemory[h8300s_reg_ini[c].addr]=h8300s_reg_ini[c].data; + } + ssr = 0x84; +} + +char *openpty(void) +{ +#if 0 + const char nm[]="0123456789ABCDEF"; + static char ptyname[16]; + int c1,c2,fd; + struct termios attr; + fd = open("/dev/ptmx",O_RDWR|O_NONBLOCK); + if(fd >= 0) { + grantpt(fd); + unlockpt(fd); + strncpy(ptyname,ptsname(fd),sizeof(ptyname)-1); + ptyname[sizeof(ptyname)-1]='\0'; + } else { + for(c1='a';c1<='z';c1++) + for(c2=0;c2= 0) { + scifd=fd; + tcgetattr(scifd,&attr); + memcpy(&old_attr,&attr,sizeof(struct termios)); + attr.c_lflag&=~ICANON; + attr.c_cc[VMIN]=0; + attr.c_cc[VTIME]=0; + tcsetattr(scifd,TCSAFLUSH,&attr); + return ptyname; + } else + return NULL; + +#else + scifd = 1; + return "stdout"; +#endif +} + +void closepty(void) +{ +#if 0 + struct termios attr; + if(scifd!=-1) { + tcsetattr(scifd,TCSAFLUSH,&old_attr); + close(scifd); + } +#endif +} diff -r -u5 -N -x '*~' insight-5.3/sim/h8300/sim-main.h insight-5.3-H8/sim/h8300/sim-main.h --- insight-5.3/sim/h8300/sim-main.h 1970-01-01 01:00:00.000000000 +0100 +++ insight-5.3-H8/sim/h8300/sim-main.h 2003-04-10 15:24:06.000000000 +0100 @@ -0,0 +1,47 @@ +/* This file is part of the program psim. + + Copyright (C) 1994-1997, Andrew Cagney + Copyright (C) 1997, Free Software Foundation + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + */ + + +#ifndef SIM_MAIN_H +#define SIM_MAIN_H + +#if 0 +#define SIM_ENGINE_HALT_HOOK(SD,LAST_CPU,CIA) 0 /* disable this hook */ +#endif + +#include "sim-basics.h" +#include "sim-signal.h" + +#include /* For kill() in insns:do_trap */ + +#include +#ifdef HAVE_UNISTD_H +#include +#endif + +typedef int sim_cia; +static const sim_cia null_cia = {0}; /* Dummy */ +#define NULL_CIA null_cia + + +#include "sim-base.h" + +#endif